Semiconductor structure having verticle conductive graphene and method for forming the same

ABSTRACT

A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has over the pastdecades experienced tremendous advancements and is still experiencingvigorous development. With the dramatic advances in IC design, newgenerations of ICs have smaller and more complex circuits. Damasceneprocess, such as single damascene or dual damascene, is one of thetechniques used for forming BEOL (back-end-of-line) interconnectstructures. The interconnect structures play an important role inminiaturization and electrical performance of the new generations ofICs. Thus, the industry pays much attention on development of theinterconnect structures.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates a process flow for making a semiconductor structurein accordance with some embodiments.

FIGS. 2 through 6 illustrate schematic views of stages in the formationof a semiconductor structure in accordance with some embodiments.

FIG. 7 is a partially enlarged view of the semiconductor structure inaccordance with some embodiments, taken from FIG. 6 .

FIG. 8 is a schematic view showing a graphene layer of the semiconductorstructure in accordance with some embodiments.

FIGS. 9 through 12 illustrate schematic views of stages in the formationof a semiconductor structure in accordance with some embodiments.

FIGS. 13 through 19 illustrate schematic views of stages in theformation of a semiconductor structure in accordance with someembodiments.

FIG. 20 is a schematic view illustrating doping/intercalation of asemiconductor structure in accordance with some embodiments.

FIGS. 21 through 27 illustrate schematic views of stages in theformation of a semiconductor structure in accordance with someembodiments.

FIG. 28 is a top view of the semiconductor structure in accordance withsome embodiments.

FIGS. 29 and 30 show semiconductor structures in accordance with someembodiments.

FIG. 31 illustrates a process of making a semiconductor structure inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the disclosure.Specific examples of components and arrangements are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. For example, the formation of afirst feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

In accordance with some embodiments, some ways of forming interconnectpatterns involve patterning dielectric layer to define desiredinterconnect openings (e.g., vias or trenches), followed by filling theinterconnect openings using deposition techniques, such as chemicalvapor deposition (CVD), atomic layer deposition (ALD), physical vapordeposition (PVD), reflow-PVD, a combination of PVD and electrochemicalplating (ECP), or the like. FIG. 31 shows a flow of an alternative wayof making a semiconductor structure. Firstly, a horizontal graphenelayer 60 is formed on a substrate 22. In some embodiments, thehorizontal graphene layer 60 has a stack of graphene sheets (not shown)with each sheet extending in a direction parallel to a top surface ofthe substrate 22. Then, the horizontal graphene layer 60 is patternedinto a plurality of separated graphene portions 61 such that thegraphene portions 61 form a pattern. Next, a dielectric layer 30 isdeposited to fill gaps between the graphene portions 61 and to cover thegraphene portions 61.

FIGS. 2 to 6 illustrate schematic views of intermediate steps in theformation of a semiconductor structure in accordance with someembodiments. The corresponding processes are also reflected in the flowchart 200 as shown in FIG. 1 .

As shown in FIG. 2 , a substrate 22 is provided. This process isillustrated as process 202 in the flow chart 200 shown in FIG. 1 . Insome embodiments, the substrate 22 may be a semiconductor substrate,e.g., an elemental semiconductor or a compound semiconductor. Anelemental semiconductor is composed of single species of atoms, such assilicon (Si) or germanium (Ge) in column 14 of the periodic table. Acompound semiconductor is composed of two or more elements, such assilicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP),indium phosphide (InP), indium arsenide (InAs), indium antimonide(InSb), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP),aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs),gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP),gallium indium arsenide phosphide (GaInAsP), or the like. The compoundsemiconductor may have a gradient feature in which the compositionthereof changes from one ratio at one location to another ratio atanother location in the compound semiconductor. The compoundsemiconductor may be formed over a silicon substrate. The compoundsemiconductor may be strained. In some embodiments, the substrate 22 mayinclude a multilayer compound semiconductor structure. Alternatively,the substrate 22 may include a non-semiconductor material, such as aglass, fused quartz, or calcium fluoride. Furthermore, in someembodiments, the substrate 22 may be a semiconductor on insulator (SOI)(e.g., silicon germanium on insulator (SGOI)). Generally, an SOIsubstrate includes a layer of a semiconductor material such as epitaxialsilicon (Si), germanium (Ge), silicon germanium (SiGe), or combinationsthereof. The substrate may be doped with a p-type dopant, such as boron(Br), aluminum (Al), gallium (Ga), or the like, or may alternatively bedoped with an n-type dopant, as is known in the art. In someembodiments, the substrate 22 may include a doped epitaxial layer.Shallow trench isolation (STI) regions (not shown) may be formed in thesubstrate 22 to isolate active regions (one is schematically shown inFIG. 2 with the numeral 24), such as a source region or a drain regionof an integrated circuit device (not shown) in the substrate 22. In someembodiments, the integrated circuit device may include transistors(e.g., field-effect transistors (FETs), complementary metal-oxidesemiconductor (CMOS) transistors, planar or vertical multi-gatetransistors (e.g., FinFET devices), gate-all-around (GAA) devices, orthe like), resistors, capacitors, diodes, interconnections, or the like,based on practical applications. In addition, through-vias (not shown)may be formed to extend into the substrate 22 for electricallyconnecting features on opposite sides of the substrate 22.

In accordance with some embodiments, a dielectric layer 26 is formedover the substrate 22, and a contact feature 28 is formed in thedielectric layer 26 and is electrically connected to the active region24.

Subsequent to the provision of the substrate 22, an etch stop layer 29is formed over the substrate 22. In some embodiments, the etch stoplayer 29 is formed on the dielectric layer 26. This process isillustrated as process 204 in the flow chart 200 shown in FIG. 1 . Insome embodiments, the etch stop layer 29 may be made of a materialselected from metal nitride, metal oxide, metal carbide, siliconnitride, silicon oxide, silicon carbide, and combinations thereof. Insome embodiments, the metal may be selected from aluminum (Al),zirconium (Zr), yttrium (Y), hafnium (Hf), zinc (Zn), and combinationsthereof. In some embodiments, the etch stop layer 29 may be formed by asuitable technique, such as CVD, plasma-enhanced CVD (PECVD), ALD,spin-on coating, electroless plating, or the like.

Subsequent to the formation of the etch stop layer 29, a dielectriclayer 30 is formed over the etch stop layer 29. This process isillustrated as process 206 in the flow chart 200 shown in FIG. 1 . Inaccordance with some embodiments, the dielectric layer 30 may be a low-kinter-layer dielectric (LK ILD) layer, such as a pre-metal dielectric(PMD) layer or an inter-metal dielectric (IMD) layer. In someembodiments, the dielectric layer 30 includes undoped silicate glass(USG), phosphosilicate glass (PSG), borosilicate glass (BSG),boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass(FSG), silicon dioxide (SiO₂), SiOC-based materials, or other suitableextreme low-K (ELK) or ultra low-K (ULK) materials. In some embodiments,silicon dioxide may be formed from tetraethyl orthosilicate (TEOS). Insome embodiments, the dielectric layer 30 may be formed using spincoating, CVD (e.g., flowable CVD, PECVD, low pressure chemical vapordeposition (LPCVD), etc.), or the like. In some embodiments, thedielectric layer 30 may include an anti-reflective layer (not shown),such as a nitrogen-free anti-reflective coating (NFARC), for preventingradiation used in a subsequent photolithographic process from reflectingoff layers below and interfering with the exposure procedure. The NFARCmay include a material such as silicon-rich oxide (SRO), or siliconoxygen carbide (i.e., carbon-doped silicon oxide). The NFARC may beformed by CVD or the like.

Referring to FIG. 3 , after the formation of the dielectric layer 30,the dielectric layer 30 and the etch stop layer 29 are patterned by anetching process to form an interconnect opening 31 in the dielectriclayer 30. In some embodiments, a top surface 281 of the contact feature28 is exposed from the interconnect opening 31. This process isillustrated as process 208 in the flow chart 200 shown in FIG. 1 . Theetching process may include a dry etching process, which includesforming a patterned mask layer (not shown) such as a patternedphoto-resist layer, and then etching the dielectric layer 30 and theetch stop layer 29 using the patterned mask layer as a mask.

In accordance with some embodiments, the interconnect opening 31 isdefined by an inner lateral surface 302 of the dielectric layer 30, andis a via 32 which extends through the dielectric layer 30 and the etchstop layer 29 and which may be formed in a single damascene process. Anopening of the interconnect opening 31 has a width (W), and theinterconnect opening 31 has a height (H). An aspect ratio of theinterconnect opening 31 is defined as H/W. In some embodiments, thewidth (W) of the opening of the interconnect opening 31 ranges fromabout 1.5 nm to about 15 nm. In some embodiments, the interconnectopening 31 may be made by a single damascene process, and the width (W)of the opening of the interconnect opening 31 ranges from about 4 nm toabout 15 nm. In some embodiments, the aspect ratio of the interconnectopening 31 is smaller than about 5.

FIG. 4 illustrates the formation of a metal layer 41 on the dielectriclayer 30. This process is illustrated as process 210 in the flow chart200 shown in FIG. 1 . In accordance with some embodiments, the metallayer 41 covers a top surface 301 of the dielectric layer 30, the innerlateral surface 302 of the dielectric layer 30, and the top surface 281of the contact feature 28 exposed from the interconnect opening 31. Insome embodiments, the metal layer 41 may be formed by PVD, CVD, ALD,electroless deposition (ELD), or the like. In some embodiments, themetal layer 41 may include Co, Ni, Ru, Rh, Pd, Re, Cu, Ag, Ir, Pt, Au,or combinations thereof. In alternative embodiments, the metal layer 41may include Ti, Hf, Ta, W, or combinations thereof. In some embodiments,the metal layer 41 may have a thickness ranging from about 0.3 nm toabout 2 nm.

FIG. 5 illustrates a process of etching away a part of the metal layer41. This process is illustrated as process 212 in the flow chart 200shown in FIG. 1 . In accordance with some embodiments, any portion ofthe metal layer 41, which is not formed on the inner lateral surface 302of the dielectric layer 30, is removed. In other words, portions of themetal layer 41 formed on the top surface 301 of the dielectric layer 30and on the top surface 281 of the contact feature 28 are removed. Themetal formed on the inner lateral surface 302 of the dielectric layer 30is maintained. In some embodiments, the etching process may be conductedusing directional dry etching, such as plasma reactive etching, atomiclayer etching, ion-beam etching, e-beam etching, plasma physicalbombardment, or the like. In some embodiments, the plasma reactiveetching may use reaction gases containing H₂, O₂, N₂, F₂, Cl₂,C_(x)F_(y), NF₃, SiF₄, SiCl₄, BCl₃, or the like. In some embodiments,the atomic layer etching may use reaction gas containing F₂, Cl₂, Br₂,H₂, HF, HCl, BCl₃, CH₃OH, HCOOH, acetylacetone, hexafluoroacetylacetone,or the like. In some embodiments, the plasma physical bombardment mayuse reaction gas containing H₂, He, Ar, N₂, Xe, or the like. The etchingprocess may involve a directional etching directed vertically toward thedielectric layer 30.

Referring to FIG. 6 with reference to FIG. 5 , a process is conducted toform a graphene conductive structure 42 on the metal layer 41 to fillthe interconnect opening 31. This process is illustrated as process 214in the flow chart 200 shown in FIG. 1 . In accordance with someembodiments, the graphene conductive structure 42 may be deposited usingPECVD with one of radio frequency (RF) plasma, direct current (DC)plasma, inductively coupled plasma (ICP), microwave (MW) plasma,electron cyclotron resonance (ECR) plasma, or the like. In alternativeembodiments, the graphene conductive structure 42 may be deposited usingthermal CVD. In some embodiments, temperature of the deposition processmay range from about room temperature to about 1000° C. In someembodiments, the graphene deposition process is PECVD to allow thedeposition to take place at a temperature below about 400° C., therebyminimizing the influence of high temperature on the integrated circuitdevice in the substrate 22. In some embodiments, precursors fordepositing the graphene conductive structure 42 may include CO, CH₄,C₂H₂, CF₄, C₂F₆, CHF₃, benzene, derivatives thereof, or the like. Insome embodiments, the metal layer 41 may serve as a catalyst for thegrowth of the graphene conductive structure 42.

FIG. 7 is a partially enlarged view taken from the dotted circle in FIG.6 . The illustrated part in FIG. 7 includes the dielectric layer 30, themetal layer 41 formed on the inner lateral surface 302 of the dielectriclayer 30, and the graphene conductive structure 42. In some embodiments,the graphene conductive structure 42 includes a plurality of graphenelayers 43 that are formed on the metal layer 41 in a layer-by-layermanner until the graphene conductive structure 42 completely fills theinterconnect opening 31 (see FIG. 5 ) without leaving voids in thegraphene conductive structure 42 as encountered in metal depositionprocess. Each of the graphene layers 43 extends in a direction (D)(e.g., a vertical direction in some embodiments) parallel to the innerlateral surface 302 of the dielectric layer 30. Each of the graphenelayers 43 may be composed of a plurality of carbon atoms arranged in ahoneycomb pattern (i.e., hexagons) extending in the direction (D) andparallel to the inner lateral surface 302 of the dielectric layer 30.One graphene layer 43 is schematically shown in FIG. 8 , in which thehoneycomb carbon layer extends in the direction (D) and parallel to theinner lateral surface 302 of the dielectric layer 30.

FIG. 9 illustrates an alternative to the structure depicted in FIG. 3and the processes 204, 206, 208 in the flow chart 200 as shown in FIG. 1. In accordance with some embodiments, another etch stop layer 35 andanother dielectric layer 36 may be formed on the dielectric layer 30.The dielectric layer 30 and the etch stop layer 29 are patterned to formthe via 32, and then the dielectric layer 36 and the etch stop layer 35are patterned to form a trench 33. In other words, the interconnectopening 31 includes the via 32, and the trench 33 which is spatiallycommunicated with the via 32 and which has a width larger than that ofthe via 32. In some embodiments, such combination of the via 32 and thetrench 33 may be formed by a dual damascene process or two separatesingle damascene processes. The via 32 and the trench 33 of theinterconnect opening 31 are defined by the inner lateral surface 302. Insome embodiments, the inner lateral surface 302 is defined by thedielectric layer 36, the etch stop layer 35, the dielectric layer 30 andthe etch stop layer 29. In some embodiments, the inner lateral surface302 is in a stepped shape, and has a first vertical portion 341 thatdefines the via 32, a second vertical portion 342 that defines thetrench 33, and a horizontal portion 343 that interconnects the firstvertical portion 341 and the second vertical portion 342. In someembodiments, the width (W) of the opening of the interconnect opening 31is defined as the width of the opening of the trench 33, and the height(H) of the interconnect opening 31 is defined as the height of the via32 and the trench 33 combined. In some embodiments, the width (W) of theopening of the trench 33 ranges from about 1.5 nm to about 15 nm. Insome embodiments, the width (W) of the opening of the trench 33 rangesfrom about 4 nm to about 15 nm. In some embodiments, the aspect ratio(H/W) of the interconnect opening 31 is smaller than about 10.

FIG. 10 illustrates an alternative to the structure depicted in FIG. 4and the process 210 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, the metal layer 41 is formed on thedielectric layer 36 and covers a top surface 361 of the dielectric layer361, the inner lateral surface 302, and the top surface 281 of thecontact feature 28 exposed from the via 32 and the trench 33 of theinterconnect opening 31. In some embodiments, the metal layer 41 may beformed by PVD, CVD, ALD, ELD, or the like. In some embodiments, themetal layer 41 may include Co, Ni, Ru, Rh, Pd, Re, Cu, Ag, Ir, Pt, Au,or combinations thereof. In alternative embodiments, the metal layer 41may include Ti, Hf, Ta, W, or combinations thereof. In some embodiments,the metal layer 41 may have a thickness ranging from about 0.3 nm toabout 2 nm.

FIG. 11 illustrates an alternative to the structure depicted in FIG. 5and the process 212 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, portions of the metal layer 41 thatare formed on the top surface 361 of the dielectric layer 36, on thehorizontal portion 343 of the inner lateral surface 302, and on the topsurface 281 of the contact feature 28 are removed. Portions of the metallayer 41 that are formed on the first vertical portion 341 and thesecond vertical portion 342 of the inner lateral surface 302 aremaintained. The etching process may be conducted using directional dryetching, such as plasma reactive etching, atomic layer etching, ion-beametching, e-beam etching, plasma physical bombardment, or the like. Insome embodiments, the plasma reactive etching may use reaction gasescontaining H₂, O₂, N₂, F₂, Cl₂, C_(x)F_(y), NF₃, SiF₄, SiCl₄, BCl₃, orthe like. In some embodiments, the atomic layer etching may use reactiongas containing F₂, Cl₂, Br₂, H₂, HF, HCl, BCl₃, CH₃OH, HCOOH,acetylacetone, hexafluoroacetylacetone, or the like. In someembodiments, the plasma physical bombardment may use reaction gascontaining H₂, He, Ar, N₂, Xe, or the like. The etching process mayinvolve a directional etching directed vertically toward the dielectriclayer 30.

FIG. 12 illustrates an alternative to the structure depicted in FIG. 6 ,and a process (i.e., the process 214 in the flow chart 200 as shown inFIG. 1 ) is conducted to form the graphene conductive structure 42 onthe metal layer 41 to fill the via 32 and the trench 33 of theinterconnect opening 31 (see FIG. 11 ). In accordance with someembodiments, the graphene conductive structure 42 may be deposited usingPECVD with one of RF plasma, DC plasma, ICP, MW plasma, ECR plasma, orthe like. In alternative embodiments, the graphene conductive structure42 may be deposited using thermal CVD. In some embodiments, temperatureof the deposition process may range from room temperature to about 1000°C. In some embodiments, the graphene deposition process isplasma-enhanced to allow the deposition to take place at a temperaturebelow about 400° C., thereby minimizing the influence of hightemperature on IC devices (not shown) in the substrate 22. In someembodiments, precursors for depositing the graphene conductive structure42 may include CO, CH₄, C₂H₂, CF₄, C₂F₆, CHF₃, benzene, derivativesthereof, or the like.

FIG. 13 illustrates an alternative to the structure depicted in FIG. 9and the process 208 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, the dielectric layer 36, the etch stoplayer 35, the dielectric layer 30 and the etch stop layer 29 arepatterned to form the interconnect opening 31, which includes the via 32and the trench 33 that is spatially communicated with the via 32 andthat has a width larger than that of the via 32. Such combination of thevia 32 and the trench 33 may be formed by a dual damascene process ortwo separate single damascene processes. The via 32 and the trench 33 ofthe interconnect opening 31 are defined by the inner lateral surface302. In some embodiments, the width (W) is defined as the width of theopening of the trench 33, and the height (H) is defined as the height ofthe via 32 and the trench 33 combined. In some embodiments, the width(W) of the opening of the trench 33 is larger than about 15 nm. In someembodiments, the aspect ratio (H/W) of the interconnect opening 31 issmaller than about 10.

FIG. 14 illustrates an alternative to the structure depicted in FIG. 10and the process 210 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, the metal layer 41 is formed on thedielectric layer 36 and covers the top surface 361 of the dielectriclayer 36, the inner lateral surface 302, and the top surface 281 of thecontact feature 28 exposed from the via 32 and the trench 33 of theinterconnect opening 31. In some embodiments, the metal layer 41 may beformed by PVD, CVD, ALD, ELD, or the like. In some embodiments, themetal layer 41 may include Co, Ni, Ru, Rh, Pd, Re, Cu, Ag, Ir, Pt, Au,or combinations thereof. In alternative embodiments, the metal layer 41may include Ti, Hf, Ta, W, or combinations thereof. In some embodiments,the metal layer 41 may have a thickness ranging from about 0.3 to about2 nm.

FIG. 15 illustrates an alternative to the structure depicted in FIG. 11and the process 212 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, portions of the metal layer 41 thatare formed on the top surface 361 of the dielectric layer 36, on thehorizontal portion 343 of the inner lateral surface 302, and on the topsurface 281 of the contact feature 28 exposed from the via 32 and thetrench 33 of the interconnect opening 31 are removed. Portions of themetal layer 41 that are formed on the first vertical portion 341 and thesecond vertical portion 342 of the inner lateral surface 302 remain. Theetching process may be conducted using directional dry etching, such asplasma reactive etching, atomic layer etching, ion-beam etching, e-beametching, plasma physical bombardment, or the like. In some embodiments,the plasma reactive etching may use reaction gases containing H₂, O₂,N₂, F₂, Cl₂, C_(x)F_(y), NF₃, SiF₄, SiCl₄, BCl₃, or the like. In someembodiments, the atomic layer etching may use reaction gas containingF₂, Cl₂, Br₂, H₂, HF, HCl, BCl₃, CH₃OH, HCOOH, acetylacetone,hexafluoroacetylacetone, or the like. In some embodiments, the plasmaphysical bombardment may use reaction gas containing H₂, He, Ar, N₂, Xe,or the like. The etching process may involve a directional etchingdirected vertically toward the dielectric layer 30.

FIG. 16 illustrates an alternative to the structure depicted in FIG. 12and the process 214 in the flow chart 200 as shown in FIG. 1 . In someembodiments, the process 214 is conducted to form the grapheneconductive structure 42 on the metal layer 41, in which the via 32 (seeFIG. 15 ) is completely filled with the graphene conductive structure 42and the trench 33 (see FIG. 15 ) is partially filled with the grapheneconductive structure 42, leaving a gap (G) in the graphene conductivestructure 42. In accordance with some embodiments, the grapheneconductive structure 42 may be deposited using PECVD with one of RFplasma, DC plasma, ICP, MW plasma, ECR plasma, or the like. Inalternative embodiments, the graphene conductive structure 42 may bedeposited using thermal CVD. In some embodiments, temperature of thedeposition process may range from about room temperature to about 1000°C. In some embodiments, the graphene deposition process isplasma-enhanced to allow the deposition to take place at a temperaturebelow about 400° C., thereby minimizing the influence of hightemperature on IC devices (not shown) in the substrate 22. In someembodiments, precursors for depositing the graphene conductive structure42 may include CO, CH₄, C₂H₂, CF₄, C₂F₆, CHF₃, benzene, derivativesthereof, or the like.

In accordance with some embodiments, as schematically illustrated inFIG. 20 , an intercalating material 50 may be doped or intercalated intothe graphene conductive structure 42, such that the electricalconductivity of the graphene conductive structure 42 may be enhanced.This process is illustrated as process 216 in the flow chart 200 shownin FIG. 1 . The doping or intercalation process may include vapor phasediffusion, CVD, PECVD, liquid phase immersion, implantation, or thelike. Some examples of the intercalating material 50 may includeTetraethylenepentamine (TEPA), Diethylenetriamine (DETA),o-Phenylenediamine (OPD), 1,2,4-Triazole, Tetraethylene glycol (TEG),Phenol, Catechol, Trifluorobenzene, Hexafluorobenzene (HFB), or thelike. Alternatively, the intercalating material 50 may be, but notlimited to, FeCl₃, MoCl₅, AuCl₃, AlCl₃, AsF₅, SbF₅, HNO₃, CuCl₂, SbCl₅,AuCl₅, NiCl₂, Cs—C₂H₄, NH₃, ZnMg, Br₂, Cl₂, H₂SO₄, their derivatives, orthe like. In some embodiments, the intercalating material 50 may includemetal, such as Li, K, Cs, Na, or the like, or their ions. In someembodiments, the intercalating material 50 may include polymer oroligomer, such as Polymethyl methacrylate (PMMA), polystyrene (PS),polycaprolactam (PA6), or the like. In some embodiments, thedoping/intercalating process is conducted at a temperature below about400° C. In some embodiments, the doping/intercalating direction of theintercalating material 50 is substantially parallel to the extendingdirection (D) of the graphene layers 43 of the graphene conductivestructure 42, thereby allowing the intercalating material 50 to beeffectively doped or intercalated into the graphene conductive structure42.

FIG. 17 illustrates a process of forming a barrier/liner layer 44 overthe dielectric layer 36. This process is illustrated as process 218 inthe flow chart 200 as shown in FIG. 1 . In some embodiments, thebarrier/liner layer 44 covers the top surface 361 of the dielectriclayer 36, top surfaces 421 of the graphene conductive structure 42, andan inner surface 422 of the graphene conductive structure 42 thatdefines the gap (G). In some embodiments, the barrier/liner layer 44includes barrier and liner. In some embodiments, the barrier of thebarrier/liner layer 44 includes TaN, TiN, Ru, MnN, ZnO, MoN, or thelike. In some embodiments, the liner of the barrier/liner layer 44includes Ta, Ti, Co, Ru, or the like. In some embodiments, the barrierof the barrier/liner layer 44 may serve to prevent metal diffusion andexudation of the metal structure formed in later steps. In someembodiments, the liner of the barrier/liner layer 44 may serve toenhance adhesion of the metal structure formed in later steps to thebarrier of the barrier/liner layer 44. In some embodiment, one of theliner and the barrier may be dispensed with. In some embodiments, thebarrier/liner layer 44 may be dispensed with.

FIG. 18 illustrates a process of forming a conductive feature 45 overthe barrier/liner layer 44 to fill the gap (G) (see FIG. 17 ). Thisprocess is illustrated as process 220 in the flow chart 200 shown inFIG. 1 . The conductive feature 45 may be made of Cu, Co, W, Ru, Mo, Al,or the like, and may be formed by PVD, reflow PVD, CVD, ALD, ELD, acombination of PVD and ECP, or the like. In some embodiments in whichthe barrier/liner layer 44 is omitted, the conductive feature 45 isdirectly formed over the dielectric layer 36 to fill the gap (G).

FIG. 19 illustrate a planarization process (e.g., chemical mechanicalpolish (CMP)) being adopted to remove portions of the conductive feature45 in excess, so as to form the conductive feature 45 filling the gap(G) (see FIG. 17 ), thereby completely filling the via 32 (see FIG. 15 )with the graphene conductive structure 42 and completely filling thetrench 33 (see FIG. 15 ) with the graphene conductive structure 42 andthe conductive feature 45. This process is illustrated as process 222 inthe flow chart 200 shown in FIG. 1 . In some embodiments, the grapheneconductive structure 42 may be doped or intercalated in process 216 insuch a manner that electrical conductivity of the graphene conductivestructure 42 matches (e.g., substantially equals) that of the conductivefeature 45.

FIG. 21 illustrates an alternative to the structure depicted in FIG. 13and the process 208 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, the dielectric layer 30 and the etchstop layer 29 are patterned (e.g., in a single damascene process) toform the interconnect opening 31 which includes the trench 33 that isdefined by the inner lateral surface 302 of the dielectric layer 30. Insome embodiments, the width (W) is defined as the width of the openingof the trench 33, and the height (H) is defined as the height of thetrench 33. In some embodiments, the width (W) of the opening of thetrench 33 is larger than about 15 nm. In some embodiments, the aspectratio (H/W) of the interconnect opening 31 is smaller than about 5.

FIG. 22 illustrates an alternative to the structure depicted in FIG. 14and the process 210 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, the metal layer 41 is formed on thedielectric layer 30, and covers the top surface 301 of the dielectriclayer 30, the inner lateral surface 302 of the dielectric layer 30, thetop surface 281 of the contact feature 28, and a top surface 261 of thedielectric layer 26 exposed from the trench 33. In some embodiments, themetal layer 41 may be formed by PVD, CVD, ALD, ELD, or the like. In someembodiments, the metal layer 41 may include Co, Ni, Ru, Rh, Pd, Re, Cu,Ag, Ir, Pt, Au, or combinations thereof. In alternative embodiments, themetal layer 41 may include Ti, Hf, Ta, W, or combinations thereof. Insome embodiments, the metal layer 41 may have a thickness ranging fromabout 0.3 nm to about 2 nm.

FIG. 23 illustrates an alternative to the structure depicted in FIG. 15and the process 212 in the flow chart 200 as shown in FIG. 1 . Inaccordance with some embodiments, any portion of the metal layer 41which is not formed on the inner lateral surface 302 of the dielectriclayer 30 is removed. In other words, portions of the metal layer 41formed on the top surface 301 of the dielectric layer 30, on the topsurface 281 of the contact feature 28 and on the top surface 261 of thedielectric layer 26 exposed from the trench 33 are removed. A portion ofthe metal layer 41 which is formed on the inner lateral surface 302 ofthe dielectric layer 30 remains. The etching process may be conductedusing directional dry etching, such as plasma reactive etching, atomiclayer etching, ion-beam etching, e-beam etching, plasma physicalbombardment, or the like. In some embodiments, the plasma reactiveetching may use reaction gases containing H₂, O₂, N₂, F₂, Cl₂,C_(x)F_(y), NF₃, SiF₄, SiCl₄, BCl₃, or the like. In some embodiments,the atomic layer etching may use reaction gas containing F₂, Cl₂, Br₂,H₂, HF, HCl, BCl₃, CH₃OH, HCOOH, acetylacetone, hexafluoroacetylacetone,or the like. In some embodiments, the plasma physical bombardment mayuse reaction gas containing Hz, He, Ar, N₂, Xe, or the like. The etchingprocess may involve a directional etching directed vertically toward thedielectric layer 30.

FIG. 24 illustrates an alternative to the structure depicted in FIG. 16and the process 212 in the flow chart 200 as shown in FIG. 1 . Is someembodiments, the process 214 is conducted to form the grapheneconductive structure 42 on the metal layer 41, in which the trench 33(see FIG. 23 ) is partially filled with the graphene conductivestructure 42, leaving the gap (G) in the graphene conductive structure42. In accordance with some embodiments, the graphene conductivestructure 42 may be deposited using PECVD with one of RF plasma, DCplasma, ICP, MW plasma, ECR plasma, or the like. In alternativeembodiments, the graphene conductive structure 42 may be deposited usingthermal CVD. In some embodiments, temperature of the deposition processmay range from about room temperature to about 1000° C. In someembodiments, the graphene deposition process is plasma-enhanced to allowthe deposition to take place at a temperature below about 400° C.,thereby minimizing the influence of high temperature on IC devices (notshown) in the substrate 22. In some embodiments, precursors fordepositing the graphene conductive structure 42 may include CO, CH₄,C₂H₂, CF₄, C₂F₆, CHF₃, benzene, derivatives thereof, or the like.

FIG. 25 illustrates an alternative to the structure depicted in FIG. 17and the process 218 in the flow chart 200 as shown in FIG. 1 . In someembodiments, the barrier/liner layer 44 covers the top surface 301 ofthe dielectric layer 30, the top surface 421 of the graphene conductivestructure 42, the inner surface 422 of the graphene conductive structure42, and the top surface 281 of the contact feature 28. In someembodiments, the top surface 261 of the dielectric layer 26 is notcompletely covered by the graphene conductive structure 42, and iscovered by the barrier/liner layer 44. In some embodiments, thebarrier/liner layer 44 includes barrier and liner. In some embodiments,the barrier of the barrier/liner layer 44 includes TaN, TiN, Ru, MnN,ZnO, MoN, or the like. In some embodiments, the liner of thebarrier/liner layer 44 includes Ta, Ti, Co, Ru, or the like. In someembodiments, the barrier of the barrier/liner layer 44 may serve toprevent metal diffusion and exudation of the metal structure formed inlater steps. In some embodiments, the liner of the barrier/liner layer44 may serve to enhance adhesion of the metal structure formed in latersteps to the barrier of the barrier/liner layer 44. In some embodiment,one of the liner and the barrier may be dispensed with. In someembodiments, the barrier/liner layer 44 may be dispensed with.

FIG. 26 illustrates an alternative to the structure depicted in FIG. 18and the process 220 in the flow chart 200 as shown in FIG. 1 . In someembodiments, the conductive feature 45 is formed over the barrier/linerlayer 44 and fills the gap (G) (see FIG. 25 ). The conductive feature 45may be made of Cu, Co, W, Ru, Mo, Al, or the like, and may be formed byPVD, reflow PVD, a combination of PVD and ECP, CVD, ALD, ELD, or thelike. In some embodiments in which the barrier/liner layer 44 isomitted, the conductive feature 45 is directly formed over thedielectric layer 30 to fill the gap (G).

FIG. 27 illustrates an alternative to the structure depicted in FIG. 19and the process 222 in the flow chart 200 as shown in FIG. 1 . In someembodiments, the planarization process (e.g., CMP) is adopted to removeportions of the conductive feature 45 in excess, so as to form theconductive feature 45 filling the gap (G) (see FIG. 25 ), therebycompletely filling the trench 33 (see FIG. 23 ) with the grapheneconductive structure 42 and the conductive feature 45.

In accordance with some embodiments, the semiconductor structureillustrated in FIG. 24 may be subjected to the doping/intercalatingprocess (as illustrated in FIG. 20 ) to increase electrical conductivityof the graphene conductive structure 42. In some embodiments, thegraphene conductive structure 42 may be doped or intercalated such thatelectrical conductivity of the graphene conductive structure 42 matches(e.g., substantially equals) that of the conductive feature 45. Withreference to FIGS. 20 and 24 , in some embodiments, thedoping/intercalating direction of the intercalating material 50 issubstantially parallel to the extending direction (D) of the graphenelayers 43 of the graphene conductive structure 42, thereby allowing theintercalating material 50 to be effectively doped or intercalated intothe graphene conductive structure 42.

FIG. 28 illustrates a top view of the semiconductor structure of FIG. 19or FIG. 27 (the top surface 361 and the dielectric layer 36 are notshown in the figure), in which the conductive feature 45 is surroundedby the barrier/liner layer 44, the graphene conductive structure 42 andthe metal layer 41.

In accordance with some embodiments, the abovementioned grapheneconductive structure may be used as a MO level conductive structure(abbreviated as MO) in BEOL interconnection. However, the grapheneconductive structure may also be applied to other layers of BEOLinterconnection, such as M1 level conductive structure, M2 levelconductive structure, etc. In some embodiments, the graphene conductivestructure may be applied to a structure for electrical interconnection(e.g., via) in semiconductor devices. In some embodiments, the grapheneconductive structure may be a via and may be connected betweenunderlying and overlying connection layers filling trenches, and each ofthe connection layers may be a graphene conductive structure or otherconductive structures made of, e.g., a metal material, such as Cu, Co,W, Ru, Mo, Al, or the like. FIG. 29 shows that the structures shown inFIGS. 6, 19 and 27 are connected to underlying connection layers 71 andoverlying connection layers 73. In some embodiments, the underlyingconnection layers 71 are formed in an underlying dielectric layer 70,and the overlying connection layers 73 are formed in an overlyingdielectric layer 72. In some embodiments, an etch stop layer 74 may beformed between the dielectric layer 36 and the overlying dielectriclayer 72. In some embodiments, each of the underlying connection layers71 may be a graphene conductive structure, a metal conductive feature,or a combination thereof. In some embodiments, each of the underlyingconnection layers 71 may be the structure shown in FIG. 6, 19 or 27 . Insome embodiments, each of the overlying connection layers 73 may be agraphene conductive structure, a metal conductive feature, or acombination thereof. In some embodiments, each of the overlyingconnection layers 73 may be the structure shown in FIG. 6, 19 or 27 .

Referring to FIG. 30 , in some embodiments in filling the interconnectopening 31 (see FIG. 22 ), processes 218 to 222 may first be performedto form the barrier/liner layer 44 and the conductive feature 45. Then,processes 210 to 214 may be performed to form the metal layer 41 and thegraphene conductive structure 42. In some embodiments, the conductivefeature 45 may be made of materials that can serve as catalyst forgrowing the graphene conductive structure 42, and may include Co, Ni,Ru, Rh, Pd, Re, Cu, Ag, Ir, Pt, Au, Ti, Hf, Ta, W, or combinationsthereof, or the like, and the metal layer 41 may be dispensed with.

The embodiments of the present disclosure have some advantageousfeatures. The graphene conductive structure according to this disclosureis directly grown in the interconnect opening from the metal layer onthe inner lateral surface and has at least one graphene layer extendingin a direction parallel to the inner lateral surface. Such grapheneconductive structure can be formed to fill the interconnect opening withsmall opening (e.g., about 1.5 nm to about 15 nm) or large aspect ratio(e.g., an aspect ratio ranging between about 5 and about 10) withoutgap-fill issues (e.g., formation of voids in metal filled in theinterconnect opening), and the graphene conductive structure and theconductive feature can be formed to fill the interconnect opening withgreater opening (e.g., an opening larger than about 15 nm) withouthaving the gap-fill issues. In addition, the graphene conductivestructure according to this disclosure has a robust covalent bondstructure, which allows the semiconductor structure to be more durable.Moreover, the graphene conductive structure provides a good electricconduction path without suffering from high resistance issues caused bygrain boundaries of some metals when the device dimension shrinks. Withthe patterned dielectric layer and metal layer, the vertical grapheneconductive structure can be easily formed into a desirable shape withoutthe need to etch the vertical graphene conductive structure.Furthermore, since doping/intercalating direction is substantiallyparallel to the extending direction of the graphene layers of thegraphene conductive structure, the intercalating material can be easilyand efficiently doped or intercalated into the graphene conductivestructure so as to improve electrical conductivity of the grapheneconductive structure or to adjust the electrical conductivity of thegraphene conductive structure to, for example, match that of theconductive feature.

In accordance with some embodiments, a semiconductor structure includesa substrate, a dielectric layer, and a graphene conductive structure.The dielectric layer is disposed on the substrate, and has an innerlateral surface that is perpendicular to the substrate. The grapheneconductive structure is formed in the dielectric layer and has at leastone graphene layer extending in a direction parallel to the innerlateral surface of the dielectric layer.

In accordance with some embodiments, a semiconductor structure includesa first dielectric layer, a conductive layer, a second dielectric layer,and a graphene conductive structure. The conductive layer is formed inthe first dielectric layer, and includes metal, graphene, or acombination thereof. The second dielectric layer is disposed on thefirst dielectric layer. The graphene conductive structure is formed inthe second dielectric layer, has at least one graphene layer extendingin a direction perpendicular to the first dielectric layer, and iselectrically connected to the conductive layer.

In accordance with some embodiments, a method of making a semiconductorstructure includes: forming a dielectric layer on a substrate; formingan interconnect opening in the dielectric layer, the interconnectopening being defined by an inner lateral surface of the dielectriclayer that is perpendicular to the substrate; and forming a grapheneconductive structure in the interconnect opening, the grapheneconductive structure having at least one graphene layer that extends ina direction parallel to the inner lateral surface.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purpose(s)and/or achieving the same advantage(s) of the embodiments introducedherein. Those skilled in the art should also realize that suchequivalent constructions do not depart from the spirit and scope of thepresent disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A semiconductor structure comprising: asubstrate; a dielectric layer disposed on the substrate, and having aninner lateral surface that is perpendicular to the substrate; and agraphene conductive structure that is formed in the dielectric layer andthat has at least one graphene layer extending in a direction parallelto the inner lateral surface of the dielectric layer.
 2. Thesemiconductor structure as claimed in claim 1, further comprising ametal layer that is connected between the inner lateral surface of thedielectric layer and the graphene conductive structure.
 3. Thesemiconductor structure as claimed in claim 2, wherein the grapheneconductive structure has a first portion and a second portion, a widthof the first portion being larger than a width of the second portion. 4.The semiconductor structure as claimed in claim 3, wherein the grapheneconductive structure has a width and a height, the width of the grapheneconductive structure being greater than about 1.5 nm, a ratio of theheight to the width being smaller than about
 10. 5. The semiconductorstructure as claimed in claim 1, further comprising a conductive featurethat is surrounded by the graphene conductive structure.
 6. Thesemiconductor structure as claimed in claim 1, wherein: the grapheneconductive structure has a first portion and a second portion, a widthof the first portion being larger than a width of the second portion;and the semiconductor structure further comprises a conductive featurethat is surrounded by the first portion of the graphene conductivestructure.
 7. The semiconductor structure as claimed in claim 6, whereinthe first portion of the graphene conductive structure has a widthgreater than about 1.5 nm, the graphene conductive structure having aheight, a ratio of the height to the width being smaller than about 10.8. The semiconductor structure as claimed in claim 1, wherein thegraphene conductive structure has a width greater than about 1.5 nm anda height, a ratio of the height to the width being smaller than about 5.9. The semiconductor structure as claimed in claim 1, wherein thegraphene conductive structure is doped with an intercalating material.10. The semiconductor structure as claimed in claim 9, wherein theintercalating material is made of tetraethylenepentamine,diethylenetriamine, o-phenylenediamine, 1,2,4-triazole, tetraethyleneglycol, phenol, catechol, trifluorobenzene, hexafluorobenzene, FeCl₃,MoCl₅, AuCl₃, AsF₅, SbF₅, HNO₃, CuCl₂, SbCl₅, AuCl₅, NiCl₂, Cs—C₂H₄,NH₃, ZnMg, or combinations thereof.
 11. The semiconductor structure asclaimed in claim 9, wherein: the semiconductor structure furthercomprises a conductive feature that is surrounded by the grapheneconductive structure; and the doped graphene conductive structure has anelectrical conductivity substantially equaling that of the conductivefeature.
 12. The semiconductor structure as claimed in claim 2, whereinthe metal layer is made of Co, Ni, Ru, Rh, Pd, Re, Cu, Ag, Ir, Pt, Au,Ti, Hf, Ta, W, or combinations thereof.
 13. A semiconductor structurecomprising: a first dielectric layer; a conductive layer that is formedin the first dielectric layer, the conductive layer including metal,graphene, or a combination thereof; a second dielectric layer disposedon the first dielectric layer; and a graphene conductive structure thatis formed in the second dielectric layer, that has at least one graphenelayer extending in a direction perpendicular to the first dielectriclayer, and that is electrically connected to the conductive layer.
 14. Amethod of making a semiconductor structure, comprising: forming adielectric layer on a substrate; forming an interconnect opening in thedielectric layer, the interconnect opening being defined by an innerlateral surface of the dielectric layer that is perpendicular to thesubstrate; and forming a graphene conductive structure in theinterconnect opening, the graphene conductive structure having at leastone graphene layer extending in a direction parallel to the innerlateral surface.
 15. The method as claimed in claim 14, furthercomprising: before the formation of the graphene conductive structure,forming a metal layer on the dielectric layer and covering the innerlateral surface; and after the formation of the metal layer and beforethe formation of the graphene conductive structure, removing a portionof the metal layer and leaving the metal layer on the inner lateralsurface.
 16. The method as claimed in claim 14, further comprisingdoping the graphene conductive structure with an intercalating material.17. The method as claimed in claim 16, wherein the intercalatingmaterial is made of tetraethylenepentamine, diethylenetriamine,o-phenylenediamine, 1,2,4-triazole, tetraethylene glycol, phenol,catechol, trifluorobenzene, hexafluorobenzene, FeCl₃, MoCl₅, AuCl₃,AsF₅, SbF₅, HNO₃, CuCl₂, SbCl₅, AuCl₅, NiCl₂, Cs—C₂H₄, NH₃, ZnMg, orcombinations thereof.
 18. The method as claimed in claim 14, furthercomprising forming a conductive feature that is surrounded by thegraphene conductive structure.
 19. The method as claimed in claim 14,wherein the interconnect opening has a via and a trench which has awidth larger than that of the via and which is in spatial communicationwith the via.
 20. The method as claimed in claim 19, further comprising:before the formation of the graphene conductive structure, forming ametal layer on the dielectric layer and covering the inner lateralsurface; and after formation of the metal layer and before the formationof the graphene conductive structure, removing a portion of the metallayer and leaving the metal layer on the inner lateral surface.